1. Field of the Invention
This invention relates to semiconductor integrated-circuit memories and, more particularly, to a static random access integrated-circuit memory(SRAM) with reduced power consumption in a read mode of operation.
2. Prior Art
Previously, reductions in power in a SRAM have been obtained by using a fabrication process with higher impedance devices and with higher thresholds to reduce current drain. Note that in this document inverted or complementary items, such as signals, are designated by adding a * character to the designation of a non-inverted item. Drawing references use an overstrike to designate an inverted item.
FIG. 1 illustrates a six transistor (6T) CMOS latch SRAM memory-cell circuit 10 that includes a first CMOS inverter pair and a second CMOS inverter pair. The first CMOS inverter pair is provided by a first PMOS transistor 12 and a first NMOS transistor 14. A source terminal of the first PMOS transistor 12 is connected to a VCC voltage terminal. A source terminal of the first NMOS transistor 14 is connected to a VSS ground terminal. An inverted output terminal 20 of the first CMOS inverter pair is connected to a drain terminal of the first NMOS transistor 14 and to a drain terminal of the first PMOS transistor 12. An input terminal 22 of the first CMOS inverter pair is connected to gate terminals of the first PMOS transistor 12 and the first NMOS transistor 14.
The second CMOS inverter pair is provided by a second PMOS transistor 24 and a second NMOS transistor 26. A source terminal of the second PMOS transistor 26 is connected to a VCC voltage terminal. A source terminal of the second NMOS transistor 24 is connected to a VSS ground terminal. An inverted output terminal 28 of the second CMOS inverter pair is connected to a drain terminal of the second NMOS transistor 26 and to a drain terminal of the second PMOS transistor 24. An input terminal 30 of the second CMOS inverter pair is connected to gate terminals of the second PMOS transistor 24 and the second NMOS transistor 26.
To provide the memory-cell latch circuit 10, the inverter pairs are cross-coupled by having the inverted output terminal 20 of the first CMOS inverter pair connected to the input terminal 30 of the second CMOS inverter pair and by having the inverted output terminal 28 of the second CMOS inverter pair connected to the input terminal 22 of the first CMOS pair.
A first gating transistor 32 connects a bitline B0 to terminals 20, 30 of the latch circuit 10. A second gating transistor 34 connects an inverted bitline B0* to the latch. The bit line B0 and the inverted bit line B0* are used to write and to read data to and from the latch circuit 10. A local word line LWL is connected to gate terminals of the gating transistors 32, 34. A positive signal on the LWL turns on gating transistors 32,34 and connects the bit line and the inverted bit line to respective output terminals 20,28 of the latch.
In a SRAM, the memory cells are arranged in rows and columns in banks of memory cells. For reading a memory cell, the bit lines and inverted bit lines are precharged to a positive voltage. When a local word line is selected, the CMOS inverter pair that has a low voltage at its output terminal pulls down the bit line or inverted bit line approximately 150 mv. At the same time, when the other CMOS inverter pair that has a high voltage at its output terminal is connected to the bit line or inverted bit line, that bit line or inverted bit line does not change voltage. For a conventional SRAM, the small 150 mv voltage differential between the bit line and the inverted bit line is then passed through a YMUX circuit to a sense amplifier, which converts the differential voltage signal to a much larger full logic-level voltage signal.
The memory cells in a particular row are addressed for reading or writing by corresponding local word lines. A local word line is bank-selected from a global wordline. All of the memory cells in a particular column of a bank share the same bit lines and inverted bit lines.
Note that a signal on the local word line LWL addresses other memory cells in other columns that are not currently connected through a YMUX circuit to a sense amplifier. For example, the local word line LWL addresses four columns that have their bit lines and inverted bit lines connected to input terminals of a 4:1 YMUX circuit. Only one of those four memory columns is hooked through a YMUX to a sense amplifier. This means that the other three memory cells are discharging their bit lines for no purpose and are wasting power in the core of a memory bank.
FIG. 2 illustrates the architecture of a prior art SRAM 50 that includes a number of memory banks that are typically illustrated as eight memory banks 0–7, with only one of the memory banks being used at a time. A typical memory core 52 is shown for bank3 and each memory bank is similarly configured. A typical memory bank3 includes a memory core, typically illustrated as 52, that has a number of the memory cell circuits, each of which, as typically illustrated in FIG. 1, is arranged in x rows and y columns. Each memory cell is addressed by a corresponding x,y address signal. Each row in a memory bank is addressed by a local word line LWL. Each memory cell in a column is connected through gating transistors in each memory cell to a bitline and an inverted bitline for that particular column of memory cells.
The SRAM 50 has a global word line decoder 54 that decodes x address signals and that provides a global word line signal on a GWL signal line 56 for corresponding word lines in the memory banks. The global word line signal is then further decoded to provide a local word line for each bank by using an appropriate bank select signal.
The SRAM 50 has a Y-decoder circuit 58 that decodes y address signals for a particular column in a particular memory bank. Each memory bank has a corresponding YMUX circuit, typically shown for memory bank 3 as 60, for selecting that particular memory column.
Assuming that each memory bank has 16 columns arranged as four groups of four columns each, the YMUX circuit 60 has four pairs of input terminals, one pair of input terminals for each pair of bit line and inverted bit line signals. Each YMUX circuit provides one of four input signals to one of a group of four differential-input sense amplifier, typically shown for the bank3 as 62. Appropriate timing and control signals for the sense amplifiers are provided by a control circuit 64. Each differential sense amplifier then provides a single-ended output bit signal to one signal line of an internal data bus 66 that has four signal lines.
Each of the memory banks has its sense amplifier located underneath the memory bank. The sense amplifier detects low-level voltages or voltage differences from a memory circuit and amplifies those low-level signals to full logic voltage levels. These low-levels signals are on the order of 150 millivolts while the full logic voltage output signals are in the order of one or more volts. The full logic voltage output signals of the sense amplifiers are then fed into the internal databus that links the various memory banks together. The internal data bus 66 provides those full logic voltage levels to output buffers and thence to output pads or terminals of the SRAM. With this arrangement, there are full high-to-low, rail-to-rail, logic voltage swings on the internal data bus.
FIG. 3 illustrates an example of a 4:1 y-multiplexer (YMUX) circuit 70 and a sense amplifier 72 used in the prior art SRAM 50 described in connection with FIG. 2. The YMUX circuit 70 has four pairs of PMOS selection transistors 80,81; 82,83; 84,85; 88,87. The drain terminals of each of the PMOS selection transistors are connected to a respective bit line or an inverted bit line of one of the four columns COL0-COL 3 of a memory core array. Respective input terminals 88, 89, 90, 91 of the YMUX circuit 70 are connected to respective gate terminals of the four pairs of PMOS selection transistors 80,81; 82,83; 84,85; 88,87. All of the output terminals of the PMOS selection transistors 80, 82, 84, 86 for bit lines are connected together at an input IN terminal of the sense amplifier 72. Similarly all of the output terminals of the PMOS selection transistors 81, 83, 85, 87 for the inverted bit lines are connected together at the inverted input IN* terminal of the sense amplifier 72. The sense amplifier 72 has a single-ended output terminal 90 that is connected to one of the bit lines of an internal data bus 92. The internal data bus is connected through a data out buffer 94 to a package pad 96. Similar circuits are provided for the other output bits.
The small 150 mv voltage differential between the bit line and the inverted bit line is passed through the YMUX circuit 70 to the sense amplifier 72. Control signals for the various sense amplifiers are passed through control lines 98a, 98b. The sense amplifier 72 provides a full rail-to-rail VSS-VDD voltage swing on the internal data bus. Using lower supply voltages for an SRAM can reduce power drain because power drain is proportional to the square of the supply voltage. Power consumed in driving a signal line in an SRAM is proportional to the signal voltage swing, the total capacitance of the signal line, and the frequency of the signals on the signal line.
A prior art SRAM with 20 output bits uses an internal data bus of 20 lines, each of which can swing from VDD to VSS. Only one pair of the PMOS selection transistors 80,81; 82,83; 84,85; 88,87 is turned on at any one time to select one of the columns COL0, COL1, COL2, COL3. As previously mentioned, a signal on a local word line LWL also addresses three other memory cells in other columns that, however, are not currently connected through the YMUX circuit 70 to the internal data bus and thence to the sense amplifier. The local word line LWL addresses four columns that all have their bit lines and inverted bit lines connected to the input terminals of the 4:1 YMUX circuit 70. However, only one of those four columns is coupled through the YMUX circuit 70 to the sense amplifier 72. This means that the other three unselected memory cells are discharging either a bit line or an inverted bit line for no purpose and are wasting power in the core.
In certain application, such as hearing aids, battery power drain is an important consideration. If less power is drawn from a hearing-aid battery, the battery will last longer before needing to be replaced. It should be appreciated that conserving any amount of battery power is important, particularly in low-power applications. For these and other applications, a need exists for a technique that reduces power drain in a SRAM during a read operation.